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IEEE EDS Japan Chapter 会員各位
IEEE EDS Kansai Chapter 会員各位
IEEE Electron Devices Society Japan Chapter
Chair 木村 紳一郎
Vice Chair 鳥海 明
IEEE EDS Minicolloquium のお知らせ
10月4日（火）5日（水）の2日に亘って、東工大と共催で
IEEE EDS Minicolloquium on Advanced Hybrid Nano Devicesを開催いたします。
皆様のご参加を頂きたくご案内申し上げます。
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日時： 2011年10月4日（火）・5日（水）
場所： 東工大蔵前会館 （http://www.somuka.titech.ac.jp/ttf/）
参加費： 無料
<プログラム>
G-COE PICE International Symposium and IEEE EDS Minicolloquium
on Advanced Hybrid Nano Devices: Prospects by World’s Leading Scientists
October 4-5, 2011, Tokyo Institute of Technology, Japan
Sponsored by Global COE Program “Photonics Integration-Core Electronics”,
Quantum Nanoelectronics Research Center, Frontier Research Center, Tokyo Institute of Technology,
Co-sponsored by FP7 NEMSIC Project and IEEE EDS Japan Chapter
Tuesday, 4 October
Opening Session
09:30 - 09:40 Kenichi. Iga (President, Tokyo Tech.) Welcome Remark
09:40 - 09:50 S. Kimura (Vice Chair, IEEE EDS Japan Chapter/ Hitachi Ltd) “Greetings from IEEE EDS”
Session 1
09:50 - 10:30 Tak H. Ning (IBM) “On SOI CMOS as Technology Platform for SoC and Hybrid Device and
Function Integration”
10:30 - 11:10 Akira Nishiyama (Toshiba) “New channel engineering for the low power CMOS technology”
11:10 - 11: 50 Carlos Diaz (TSMC) “Power-constrained era -- implications on Logic Technologies"
11:50 - 13: 00 Lunch Break
Session 2
13:00 - 13: 40 Dim-Lee Kwong (IME, Singapore) “Bringing the Benefits of Moore's Law to Medicine”
13:40 - 14: 20 Simon Deleonibus (LETI, France) “Challenges and Opportunities of Technologies and
Components for Diversified Future Silicon Platforms”.
14:20 - 15: 00 Cor Claeys (IMEC) “Nanoelectronics as Innovation Driver for a Green Sustainable World”
15:00 - 15:15 Break
Session 3
15:15 -15:50 Hiromichi Ohashi (AIST), “Role of Nano-technology for Integrated Power Electronics System”
15:50- 16:25 Hitoshi Wakabayashi (Sony), “CMOS-Device Technology Benchmarks for Low-Power Logic LSIs”
16:25 -16:55 Ken Uchida (Tokyo Tech.) “Carrier mobility in heavily-doped nanoscale SOI films”
16:55 -17:30 Hiroshi Iwai (Tokyo Tech.) “Miniaturization and future prospects of Si devices”
Poster session 1
17:30-18:30 Poster Presentation
18:30-20:30 Reception at Royal Blue Hall
Wednesday, 5 October
Session 4
09:15 - 10:00 Hiroyuki Fujita (U. Tokyo) “MEMS Integration with CMOS and Beyond”
10:00 - 10:30 Joost Van Beek (NXP) “Sensors and actuators at NXP: bringing more than Moore to CMOS”
10:30 - 10:45 Break
Session 5
10:45 - 11:15 Kazuya Masu (Tokyo Tech.) Challenges of Heterogeneous Integration on CMOS
11:15 - 11:45 William I. Milne (Cambridge Univ) “ZnO Based SAW and FBAR devices for Lab-on-a chip
Applications”
11:45 - 12:15 Shunri Oda (Tokyo Tech.) “NeoSilicon based nanoelectromechanical information devices”
12:15 - 13:00 Lunch Break
Session 6
13:30 - 13:50 Adrian Ionescu (EPFL) “Overview of NEMSIC project: low power integrated sensing with
Nano-Electro-Mechanical structures”
13:50 - 14:10 Hiroshi Mizuta (Southampton) “Silicon nanowires for advanced sensing: Electrical and
electromechanical characteristics and functionalisation technology”
14:10 - 14:30 Julia Pettine (IMEC-NL) “Circuit design for NEMS/MEMS resonator gas sensors”
14:30 - 14:50 Sorin Cotofana (Delft) "Advanced NEMFET-based Power Management for Deep Sub-Micron
Integrated Circuits"
14:50 - 15:10 Daniel Bertrand (HIQSCREEN) “From biology to NEMS: the importance of new sensor developments”
15:10 - 15:30 Eric Ollier (CEA-LETI) “TBD”
15:30 - 16:00 Cornel Cobianu (Honeywell, Romania) “A possible roadmap for NEMS sensors”
Poster session 2
16:00 - 16:45 Poster Presentation
Session 7
16:45 - 17:15 Adrian Ionescu (EPFL) “Guardian Angels for a Smarter life -- 1 Billion Euros for Zero Power”
17:15 - 18:00 Panel discussion
18:00 - 18:15 Closing Remarks and Best Poster Awards Presentation
Poster Session (October 4, Tuesday, 15:00~16:00, October 5, Wednesday, 16:00~16:45)
P-1. Ian C. Robertson, Tetsuo Kodera, Yasuko Yanagida, Ken Uchida, and Shunri Oda : “Utilizing 2D figures of DNA
polymer for self-assembly applications on silicon platform”
P-2. Muhammad Amin Sulthoni, Tetsuo Kodera, Yukio Kawano, and Shunri Oda : “Transport Simulation of an
Electrostatically Defined Silicon Double Quantum Dot Device”
P-3. Yoshifumi Nakamine, Ken Someno, Hiroki Nikaido, Masahiro Kouge, Tetsuo Kodera, Yukio Kawano, Ken Uchida,
Mutsuko Hatano, and Shunri Oda : “Evaluation of Electrical and Optical Property and High-Density Assembly of
Nano-Crystalline Silicon Dot Array for Device Application”
P-4. Jean Tarun, Shaoyun Huang, Yasuhiro Fukuma, Hiroshi Idzuchi, Yoshichika Otani, Tetsuo Kodera, Naoki Fukata,
Koji Ishibashi, and Shunri Oda : “Low-Temperature Magnetoresistance Studies of Silicon Nanowires with Permalloy
Leads”
P-5. Tomohiro Kambara, Tetsuo Kodera, Thierry Ferrus, Alessandro Rossi, Kosuke Horibe, Yasuhiko Arakawa, David
Williams, and Shunri Oda : “Charge detection techniques in Si double quantum dots”
P-6. Marolop Simanullang, Koichi Usami, Tetsuo Kodera, Ken Uchida, Shunri Oda : “Synthesis of small-diameter Ge
NW at low temperature for electron device application”
P-7. Ayse Seyhan, Yoshi Ogawa, Maralop Simanullang and Shunri Oda : “Photoluminescence and Raman studies of
Ge nanowires grown on Si (100) and (111) substrates”
P-8. Ken Someno, Kouichi Usami, Tetsuo Kodera, Yukio Kawano, Mutsuko Hatano, and Shunri Oda : “Photoluminescence
of Nanocrystalline Silicon Quantum Dots prepared by VHF Plasma”
P-9. Tomotaka Sawada, Testuo Kodera, Yuki Kawano, Mustuko Hatano, and Shunri Oda : “Electron transport in a
single silicon nanocrystal between nanogap electrodes”
P-10. Y. Fukuoka, T. Kodera, K. Takeda, T. Obata, K. Yoshida, T. Otsuka, K. Sawano, K Uchida, Y. Shiraki, S.
Tarucha, and S. Oda : “Pd Schottky gate operation voltage of Si/SiGe quantum-point-contact”
P-11. K. Horibe, T. Kodera, T. Kambara, K. Uchida, S. Oda : “Fabrication of few-electron silicon quantum dot
devices based on an SOI substrate with a top gate cintact”
P-12. T. Kodera, K. Horibe, W. Lin, T. Kambara, T. Ferrus, A. Rossi, K. Uchida, D. A. Williams, Y. Arakawa, and
S. Oda : “Development of silicon quantum dot devices toward spin quantum bits”
P-13. Berrin Pinar Algul and Ken Uchida : “Optimization of Source/Drain Doping Concentration of Carbon Nanotube
FETs to Suppress Off-state Leakage Current while Keeping Ideal On-state Current”
P-14. Tsunaki Takahashi, Tetsuo Kodera, Shunri Oda, and Ken Uchida : “Direct Observation of Subband Structures
in (110) Si pMOSFETs under High Magnetic Field and Its Impact on Hole Transport”
P-15. Teruyuki Ohashi, Naotoshi Kadotani, Tsunaki Takahashi, Shunri Oda and Ken Uchida : “Mechanisms of electron
mobility enhancement in junctionless SOI MOSFETs”
P-16. Nobuyasu Beppu, Tsunaki Takahashi, Teruyuki Ohashi and Ken Uchida : “Accurate Evaluation of Self-Heating
Effects in SOI MOSFETs with Four-point Gate Resistance Measurement Method”
P-17. A. Teranishi, K. Shizuno, S. Suzuki, M. Asada, H. Sugiyama, and H. Yokoyama : “Fundamental Oscillation
up to 1.08 THz in Resonant Tunneling Diodes with High Indium Composition Transit Layers”
P-18. M. Hosoda, Y. Lee, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T. Hattori, and
H. Iwai (Tokyo Tech.): “Size dependent phonon limited electron mobility of Si nanowire”
P-19. A. Abudukelimu, A. Ablimit*, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T. Hattori, and
H. Iwai (Tokyo Tech. *Xinjiang University): “Electron transport in ballistic diodes: influence of phonon generation in
drain region”
P-20. K. Matsumoto, M. Koyama, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T. Hattori,
and H. Iwai (Tokyo Tech.): “Ni silicidation for Si fin and nanowire structures”
P-21. C. Dou, S. Sato, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T. Hattori, and H.
Iwai (Tokyo Tech.): “Si nanowire FET with asymmetric channel”
P-22. K. Nakajima, W. Li, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T. Hattori, and H. Iwai
(Tokyo Tech.):“Interface state density measurements of 3D silicon channel by charge pumping method”
P-23. W. Li, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T. Hattori, and H. Iwai (Tokyo Tech.):
“Interface state density measurements of 3D silicon channel by charge pumping method”
P-24. Y. Tamura, R. Yoshihara, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T. Hattori, and H. Iwai
(Tokyo Tech.):“A novel Ni silicidation technology for Schottky diode formation”
P-25. R. Yoshihara, Y. Tamura, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T. Hattori, and H. Iwai
(Tokyo Tech.):“Electrical characterization of atomically flat NiSi2 Schottky diode”
P-26. D. H. Zadeh, Y. Suzuki, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T. Hattori, and H. Iwai
(Tokyo Tech.):“Characterization of metal Schottky junction for InGaAs substrate”
P-27. R. Hosoi, Y. Suzuki, D. H. Zadeh, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T. Hattori, and
H. Iwai (Tokyo Tech.): “A novel interpretation of frequency dispersed capacitances in InGaAs capacitor by conductance method”
P-28. M. Mamat, T. Seki, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T. Hattori, and H. Iwai
(Tokyo Tech.):“Evaluation of oxide traps in La based oxides for direct high-k/Si capacitor”
P-29. K. Tuokedaerhan, T. Kaneda, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T. Hattori, and
H. Iwai (Tokyo Tech.): “Impact of annealing ambient for La2O3/Si capacitor”
P-30. M. Kouda, K. Ozawa, K. Kakushima, P. Ahmet, H. Iwai, and T. Yasuda* (Tokyo Tech., *AIST): “Comparative study of
CeO2 gate dielectrics using chemical vapor deposition and atomic layer deposition”
P-31. T. Suzuki, M. Kouda, K. Kakushima, P. Ahmet, H. Iwai, and T. Yasuda* (Tokyo Tech., *AIST): “Formation and electrical
characterization of MgO - incorporated La2O3 gate insulators by ALD”
P-32. K. Tsuneishi, M. Kouda, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T. Hattori, and H. Iwai
(Tokyo Tech.): “Electrical properties of Tm2O3 gate dielectric and its scaling issues”
P-33. T. Kawanago, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T. Hattori, and H. Iwai (Tokyo Tech.):
“Nitrogen incorporated La-silicate gate dielectric with high scalability”
P-34. D. Kitayama, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T. Hattori, and H. Iwai (Tokyo Tech.):
“Effect of Silicate Formation at Metal Gate/High-k Interface on Electrical Characteristics of La2O3 gated MOS Devices”
P-35. S. Kano, C. Dou, M. Hadi, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T. Hattori, and
H. Iwai (Tokyo Tech.): “Impact of metal electrode material on resistive switching properties of Ce oxides”
P-36. Y. Wu, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T. Hattori, and H. Iwai (Tokyo Tech.):
“An analytical model of a tunnel FET with Schottky junction”
P-37. Y. Tanaka, K. Kakushima, P. Ahmet, A. Nishiyama, N. Sugii, K. Tsutsui, K. Natori, T. Hattori, and H. Iwai (Tokyo Tech.):
“Impact of annealing on structural change in amorphous carbon: effect of Fe catalyst”
P-38. K. Kakushima, J. Kanehara, T. Hattori, K. Tsutsui, and H. Iwai (Tokyo Tech.): “Boron depth profile of a plasma immersed
substrate by XPS analysis”
P-39. Y. Takamura, and S. Sugahara (Tokyo Tech.): “Analysis and design of Hanle-effect spin-transistor”
P-40. Y. Takamura, K. Hayashi, S. Shuto, and S. Sugahara (Tokyo Tech.): “Formation and structural analysis of half-metallic
Co2FeSi/SiOxNy/Si contacts with radical-oxynitridation-SiOxNy tunnel barrier”
P-41. M. Satoh, Y. Takamura, and S. Sugahara (Tokyo Tech.): “Preparation and characterization of L21-ordered full-Heusler
Co2FeSi1-xAlx alloy thin films formed by rapid thermal annealing”
P-42. T. Okishio, Y. Takamura, and S. Sugahara (Tokyo Tech.): “Low-barrier ferromagnet source/drain MOSFETs using
CoFe/Mg/AlOx/Si depinning contacts”
P-43. Y. Shuto, S. Yamamoto, and S. Sugahara (Tokyo Tech.): “Nonvolatile SRAM based on spin-transistor architecture for
nonvolatile power-gating systems”
P-44. S. Yamamoto, Y. Shuto, and S. Sugahara (Tokyo Tech.): “Nonvolatile power-gating FPGAs based on spin-transistor
architecture”
P-45. J. Kanehara, Y. Takei, Y. Miyata, H. Nohira*1, Y. Izumi*2, T. Muro*2, T. Kinoshita*2, P. Ahmet, K. Kakushima,
K. Tsutsui, T. Hattori, and H. Iwai (Tokyo Tech., *1Tokyo City Univ., *2JASRI): “Depth Profiling of As with Various Chemical
Bonding States Doped in Si Shallow Junction by Using Soft X-ray Photoelectron Spectroscopy”
P-46. Y. Miyata, K. Akita, J. Kanehara, H. Nohira*1, Y. Izumi*2, T. Muro*2, T. Kinoshita*2, P. Ahmet, K. Kakushima,
K. Tsutsui, T. Hattori, and H. Iwai (Tokyo Tech., *1Tokyo City Univ., *2JASRI): “Analysis of Boron Doped in Si Fin Structure
by Soft X-ray Photoelectron Spectroscopy”
P-47. K. Takahashi, T. Tamura, Y. Hayashi, R. Kayanuma, and K. Tsutsui (Tokyo Tech.): “Study of Leakage Current Depending on
Alloy Composition in Epitaxial Fluoride Thin Insulator Layers Grown on Ge Substrates”
P-48. R. Kayanuma, S. Namba, K. Takahashi, and K. Tsutsui (Tokyo Tech.): “Fluoride Heterostructures on Si with Epitaxial Silicide
Layers for Chemical Reaction Control”
P-49. Y. Hayashi, K. Takahashi, and K. Tsutsui (Tokyo Tech.): “Low Temperature Growth of CaF2 Layers with Low Leakage
Current on Si Substrates”
P-50. K. Uryu and M. Watanabe (Tokyo Tech.): “Retention characteristics of resistance switching memory using Si/CaF2/CdF2
quantum-well structures”
P-51. C. Koseki and M. Watanabe (Tokyo Tech.): “Fabrication of p-i-n cell structure using CaF2/Si quantum-dot superlattice”
P-52. T. Sano, D.H. Han, and S. Ohmi (Tokyo Tech.): “Investigation of Substrate Orientation and Initial Surface Roughness
Dependence of HfN/HfSiON Gate Stacks”
P-53. M. Liao, H. Ishiwara, and S. Ohmi (Tokyo Tech.): “Room temperature fabrication of HfON gate insulator for low-voltage
operating pentacene-based organic field-effect transistors”
P-54. H. Han and S. Ohmi (Tokyo Tech.): “Effect of Post Deposition Annealing on Electrical Characteristics of Hf-Nitride
Gate Insulator”
P-55. D.H. Han and S. Ohmi (Tokyo Tech.): “Effect of Si surface roughness on electrical characteristics of HfON gate insulator”
P-56. T. Ohnishi, T. Sano, and S. Ohmi (Tokyo Tech.): “Effect of Nitrogen Concentration of HfxNy for HfON Formation Utilizing
ECR Plasma Oxidation”
P-57. K. Kamino, H. Ishiwara, and S. Ohmi (Tokyo Tech.): “Fabrication of Pentacene based OFETs utilizing ultra-thin PVP
interfacial layer formed by thermal evaporation”
P-58. Nakajima Akira*1, Yasunobu Sumida*2, Mahesh H. Dhyani*3, Shuichi Yagi*2, Hiroji Kawai*2, E. M. Sankara Narayanan3
(*1AIST, *2POWDEC K. K., *3University of Sheffield): “Polarization junction concept for next generation GaN power devices”
以上
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＜現地連絡先＞
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東京工業大学 フロンティア研究機構
岩 井 洋
〒226-8502 横浜市緑区長津田町4259
Mail-Box：J2-68
TEL:045-924-5471
FAX:045-924-5584
E-mail:iwai.h.aa@m.titech.ac.jp
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IEEE EDS Japan Chapter連絡先:Secretary 鳥居 和功
E-mail:kazuyoshi.torii@ieee.org
Home page:http://www.ieee-jp.org/section/tokyo/chapter/ED-15/
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